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Scarlet's avatar
Scarlet
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1 year ago

High-speed transmission interface at around 3 meters for FPGA to FPGA communication

Hi, I’m looking for a high-speed transmission interface at around 3 meters for FPGA to FPGA communication. My development environment: MAX10 10m08sae144c8g Quartus Prime Lite 23.1.1 Currently,...
Compilation
Hdl
Simulation
Timing
FvM's avatar
FvM
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1 year ago
Your receiver is missing a frame synchronization mechanism.
  • Scarlet's avatar
    Scarlet
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    1 year ago

    Indeed, I have found that there is no frame synchronization.

    My initial judgment is that during FPGA power-up, it has led to a misjudgment of the rising edge of the LVDS clock.

    I would like to ask if, generally, when using LVDS for transmission and reception, is it necessary to have a signal line to determine Enable?

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      1 year ago
      LVDS is an IO standard, not a transmission protocol. If you use a SPI like protocol, you'll have clock, enable and data lines. You can also use UART style asynchronous protocol with start/stop bits. Or synchronous protocol with sync pattern. A popular method is 8b/10b encoding, receive clock derived from data stream by CDR circuit.
      • Scarlet's avatar
        Scarlet
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        1 year ago

        Yes, I understand that LVDS is only the Physical Layer in the OSI Model.

        During the initial design, I found that there are synchronous methods involving a clock for transmission and asynchronous methods, like UART, that do not use a clock.

        So, I designed a simple reception method. However, it seems to be encountering issues.