Help with internal Clock and States

Hi, I am very knew to Verilog and coding in general. I have to build a state machine so that when I have an input, the internal clock doesnt register it more then once. Instead it will pulse an output for one clock cycle. In order to do this I need to implement Input Conditioning. So there will be what I believe to be 5 states.

A: input 0,clock 0 or 1, output 0

B: input 1, clock 0, output 0

C: input 1, clock 1, output 1

D: input 1 or 0, clock 0, output 1

E: input 1 or 0, clock 1, output 0

I wrote some code which I believe is correct. My main area of concern is when I start the second Always block, the clk isn't posedge in the brackets, because the compiler wouldnt let me do it otherwise. The code compiles, but in the simulator there seems to be no change in the output regardles of inputs.

module attempt3(clk, a, reset, out);

input clk, a, reset;

output out;

reg out;

reg [1:0] state;

parameter A=0, B=1, C=2, D=3, E=4;

always @(state)

begin

case (state)

A:

out = 0;

B:

out = 0;

C:

out = 1;

D:

out = 1;

E:

out = 0;

endcase

end

always @(a, clk, reset)

begin

if (reset)

state = A;

else

case (state)

A:

if (a==0)

state = A;

else

state = B;

B:

if (a==0)

state = A;

else if (clk==0)

state = B;

else

state = C;

C:

if (clk==0)

state = D;

else

state = C;

D:

if (a==0)

state = A;

else

state = E;

E:

if (a==0)

state = A;

else

state = E;

endcase

end

endmodule

Thanks for any advice!