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Altera_Forum's avatar
Altera_Forum
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12 years ago

Help with internal Clock and States

Hi, I am very knew to Verilog and coding in general. I have to build a state machine so that when I have an input, the internal clock doesnt register it more then once. Instead it will pulse an outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanks for the help Alex, but I realized I mad one vital mistake when making the thread, I posted the wrong code :(. Anyway I have update my OP with the right code. I'll start reading the link you posted.