Help with internal Clock and States

I suspect your test bench is at fault. I have simulated your code and can see activity on your 'out' signal, except out[3]. However, your code doesn't change that value. So, that's as expected. I've attached my test bench code for reference.

You suggest you're new to this and, perhaps, your code demonstrates that :cool:. I have to recommend you have a good read through some form of verilog training. There is plenty of help online. You'll not go far wrong having a good read through the following:

http://www.asic-world.com/verilog/index.html (http://www.asic-world.com/verilog/index.html)

Perfect for starters, perhaps lacks a little for the more advanced designer.

Regards,

Alex