Help in Verilog Code: Edge Trigger

I am working with Altera Cyclone V FPGA Board.

Design Goal : I need to run counter using SOPC and NIOS

Design Process:

Using Verilog Code

1. Generating Trigger for 500ns
2. Generating Counter data

Help: I need to collect the counter data only at positive edge of Trigger signal (not at entire positive cycle of Trigger signal).

module Counter(
      input clk,               // Clk: 50 Mhz
	input enable,
    input reset,
    output reg[31:0] Final_value,
    output  reg trig
    );
    reg[31:0] counter_out;
    reg [7:0] temp=0;
    wire detect;
    reg [31:0] counter_result;
    reg temp1;
    wire temp2;
       
   always@(posedge clk)
   begin
    if(reset)
        begin
        trig<=0;
        temp<=0;
        counter_out<=0;
        end
    else if (enable==1'b1)
        begin
        counter_out<=counter_out+1;
        temp<=temp+1;
        if(temp==25)
            begin
            temp<=0;
            trig<=~trig;
            temp1<=trig;             // Generating Trigger for 500ns
            end
		  end
  end 
 
	 assign temp2=temp1&&clk;
	 always@(posedge temp2)
	 if(reset)
	    counter_result<=0;   
	  else 
	 begin
        counter_result<=counter_result+1;                    // Increaming the Counter
     end
   assign detect = counter_result & ~temp1;             // Positive Edge detect of Trigger
   always@(posedge detect)
   if(reset)
   Final_value<=0;  
   else 
   begin
   Final_value<=counter_result;
   end
   
endmodule

I have tried but its not giving the correct results!