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SS5
Occasional Contributor
Occasional ContributorHelp in Verilog Code: Edge Trigger
I am working with Altera Cyclone V FPGA Board. Design Goal : I need to run counter using SOPC and NIOS Design Process: Using Verilog Code Generating Trigger for 500ns Generating Counter data ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
If you use posedge trig, the signal will be latched at the positive edge of the clock signal (trig) within the setup and hold window but not the entire positive cycle of the clock.
Thanks.
