Forum Discussion
SS5
Occasional Contributor
Occasional ContributorHelp in Verilog Code: Edge Trigger
I am working with Altera Cyclone V FPGA Board. Design Goal : I need to run counter using SOPC and NIOS Design Process: Using Verilog Code Generating Trigger for 500ns Generating Counter data ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
I need to collect the counter data only at positive edge of Trigger signal (not at entire positive cycle of Trigger signal).
Could you elaborate? Does counter data refer to Final value? What is Trigger in this verilog code (trig or temp 1 or temp 2) ?
