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SS5's avatar
SS5
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Help in Verilog Code: Edge Trigger

I am working with Altera Cyclone V FPGA Board. Design Goal : I need to run counter using SOPC and NIOS Design Process: Using Verilog Code Generating Trigger for 500ns Generating Counter data ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

I need to collect the counter data only at positive edge of Trigger signal (not at entire positive cycle of Trigger signal).

Could you elaborate? Does counter data refer to Final value? What is Trigger in this verilog code (trig or temp 1 or temp 2) ?