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SS5
Occasional Contributor
Occasional ContributorHelp in Verilog Code: Edge Trigger
I am working with Altera Cyclone V FPGA Board. Design Goal : I need to run counter using SOPC and NIOS Design Process: Using Verilog Code Generating Trigger for 500ns Generating Counter data ...
SS5Occasional Contributor
Occasional ContributorHello,
>>Does counter_result refer to Final value? Yes, But putting counter date at an edge value of Trigger into Final value reg.
>>What is Trigger in this verilog code (trig or temp 1 or temp 2) ?
trig
delay trig--- temp1
Please refer this link for detailed explanation
