help!!! A simple question of a verilog fresh man

i have typed the following codes into" .v file"

but after compiled , the compiler showed me:" Error: Can't synthesize current design -- Top partition does not contain any logic"

but i have make it the top level through "Project->Set top_level Entity "

it still can't be solved ~~please help :p

codes:

module myand(a, b, c);

// Input Port(s)

input a,b;

// Output Port(s)

output c;

assign c=a&b;

// Additional Module Item(s)

endmodule