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Altera_Forum's avatar
Altera_Forum
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14 years ago

help!!! A simple question of a verilog fresh man

i have typed the following codes into" .v file" but after compiled , the compiler showed me:" Error: Can't synthesize current design -- Top partition does not contain any logic" but i have m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Hi,

check whether your toplevel is set to to "myand". have look to the attahed project.

kind regards

GPK

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thank you ,i will try it ~:)