Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

Hi @KhaiY_Intel​ ,

No, most of the warnings relate to Altera IP code such as FIFO, EPCS controller, NIOS, so I can't change the design.

Thank you.

Hi Hi ACoga,

Do you mind to share the design?

Thanks

It's possible. How can I do it?

Hi YY,

Unfortunately, I have restrictions to share the design...

Do you have any ideas what can I check to get rid of these warnings?

Thank you.

Thank you very much @KhaiY_Intel​ , great explanations. I'll try to overconstrain, but it looks that I have a problem with some settings. The warnings don't look real - all of them from and to the same node...

Hi @KhaiY_Intel​ ,

I haven't solved it yet. Not really clear how to overconstrain the hold warnings of the same clock To and From the same signal. The number of the warnings (I could see a few hundreds of them and don't know the exact number - could be much higher) makes me think that something basic is wrong.

I've tried to remove the .sdc file and leave only derive_pll_clocks, but this type of warnings still appears, so it is not the .sdc file issue.

I'm working with Quartus 16.1, someone advised me to try a newer version. I can try it on the next week.

If you have any new ideas, I'll appreciate it.

Thank you.