Forum Discussion
ACoga
New Contributor
7 years agoHello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.
Most of the signals relate to NIOS. The design based on a single 100MHz clock. There is an additional clock 12.5MHz generated in pll in QSYS and connected only to epcs flash controller. I've seen sim...
KhaiChein_Y_Intel
Regular Contributor
7 years agoHi Hi ACoga,
Do you mind to share the design?
Thanks