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ACoga's avatar
ACoga
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7 years ago

Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

Most of the signals relate to NIOS. The design based on a single 100MHz clock. There is an additional clock 12.5MHz generated in pll in QSYS and connected only to epcs flash controller. I've seen sim...
ACoga's avatar
ACoga
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7 years ago

Hi @KhaiY_Intel​ ,

I haven't solved it yet. Not really clear how to overconstrain the hold warnings of the same clock To and From the same signal. The number of the warnings (I could see a few hundreds of them and don't know the exact number - could be much higher) makes me think that something basic is wrong.

I've tried to remove the .sdc file and leave only derive_pll_clocks, but this type of warnings still appears, so it is not the .sdc file issue.

I'm working with Quartus 16.1, someone advised me to try a newer version. I can try it on the next week.

If you have any new ideas, I'll appreciate it.

Thank you.