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ACoga
New Contributor
New ContributorHello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.
Most of the signals relate to NIOS. The design based on a single 100MHz clock. There is an additional clock 12.5MHz generated in pll in QSYS and connected only to epcs flash controller. I've seen sim...
ACogaNew Contributor
New ContributorThank you very much @KhaiY_Intel , great explanations. I'll try to overconstrain, but it looks that I have a problem with some settings. The warnings don't look real - all of them from and to the same node...
