Occasional ContributorGet warnings when constraining Clock and Generated clocks
am trying to build the following.clock circuits. Although it works, I am not able to get the constraints to work:
Basically I have a 20 MHz input clock. This generates an 80 MHz clock which in turn is used to generate a 320MHz. The 80 MHz clock is used elsewhere in the design. There are other clocks derived, but I basically I hope that if I can get theese two to work, I can figure out the others.
clock : clock_src
port map(locked => reset_n,
outclk_0 => clk_80mhz,
outclk_1 => clk_75mhz,
outclk_2 => clk_80mhz_shift,
refclk => FPGA_MASTER_CLK,
rst => L0);
h_pll : highlands_pll
port map (locked => open,
outclk_0 => clk320_mhz,
outclk_1 => clk25_6mhz,
refclk => clk_80mhz,
rst => reset);
Both pll's are Integer mode
I set the following constraints :
create_clock -name {FPGA_MASTER_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {FPGA_MASTER_CLK}]
create_generated_clock -name {clk_80mhz} -source [get_ports {FPGA_MASTER_CLK}] -multiply_by 4 -master_clock {FPGA_MASTER_CLK} [get_pins {clock|clock_src_inst|altera_pll_i|outclk_wire[0]~CLKENA0|outclk}]
create_generated_clock -name {clk320_mhz} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -multiply_by 4 -master_clock {clk_80mhz} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|outclk_wire[0]~CLKENA0|outclk}]
When I compile I get the following message:
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 50.000
Warning (332056): Node: h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 12.500
What am I doing wrong?
I am using Quartus standard for cyclone V
