Occasional Contributor
Regular ContributorHi,
The warning is on the PLL's internal VCO, which we don't constraint. There is no impact on the output clock.
Best is to apply use following two constraints:
1) create_clock -name {FPGA_MASTER_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports {FPGA_MASTER_CLK}]
2) derive_pll_clocks
The constraint derive_pll_clocks automatically derives the PLL output clocks based on the settings made in the IP. This helps user to get rid of the create_generated_clock constraints on the PLL outputs.
After applying derive_pll_clocks constraint, check the Fitter report. You will find below info:
Info (332111): Found 8 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 0.833 clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
Info (332111): 12.500 clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332111): 13.333 clock|clock_src_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332111): 12.500 clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332111): 50.000 FPGA_MASTER_CLK
Info (332111): 1.562 h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
Info (332111): 3.125 h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332111): 39.062 h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk
Note in the above, the tool automatically identified the clocks which it was complaining about.
More details on derive_pll_clocks can be found in Intel Quartus Prime Standard Edition User Guide: Timing Analyzer https://www.intel.com/content/www/us/en/programmable/documentation/ony1529966370740.html#mwh1412203472219
Regards.
Occasional ContributorI used the GUI to create the clocks. So yes, I did use the name finder.
I used use derive_pll_clocks and got the following:
create_generated_clock -name {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 32 -divide_by 2 -master_clock {FPGA_MASTER_CLK} [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -phase 90/1 -master_clock {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 2 -master_clock {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
create_generated_clock -name {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
create_generated_clock -name {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 25 -master_clock {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
The clocks output by clock_src are:
outclk_0 = clk_80mhz
outclk_1 = clk_75mhz
outclk_2 = clk_80mhz_shift
of which clk_80mhz is used as both a clock and the reference clock for highlands_pll
clk_75mhz is not connected to anything in this design
clk_80mhz_shift is a 90 degree shift of clk_80mhz which is not 8used as a clock in the FPGA but is output to clock other ICs.
The clocks outputs of highlands_pll are:
outclk_0 = clk320_mhz
outclk_1 = clk25_6mhz
where both clk320_mhz and clk25_6mhz are used as clock in the FPGA
how do these clock names correspond to names in the derived clocks?
