Get warnings when constraining Clock and Generated clocks

Map them this way:

clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] --> Internal VCO of clock_src

clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_0 of clock_src

clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_2 of clock_src

h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] --> Internal VCO of highlands_pll

h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_0 of highlands_pll

h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk --> outclk_1 of highlands_pll

Now substitute in constraint:

create_generated_clock -name {Internal VCO of clock_src} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 32 -divide_by 2 -master_clock {FPGA_MASTER_CLK} [get_pins {Internal VCO of clock_src}]

This is (20*32)/2 = 320 MHz (internal)

create_generated_clock -name {outclk_0 of clock_src} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -master_clock {Internal VCO of clock_src} [get_pins {outclk_0 of clock_src}]

This is (320*1)/4 = 80 MHz

create_generated_clock -name {outclk_2 of clock_src} -source [get_pins {clock|clock_src_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 4 -phase 90/1 -master_clock {Internal VCO of clock_src} [get_pins {outclk_2 of clock_src}]

This is (320*1)/4 = 80 MHz with 90 degree phase shift

create_generated_clock -name {Internal VCO of highlands_pll} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 16 -divide_by 2 -master_clock {outclk_0 of clock_src} [get_pins {Internal VCO of highlands_pll}]

This is (80*16)/2 = 640 MHz (internal)

create_generated_clock -name {outclk_0 of highlands_pll} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 2 -master_clock {Internal VCO of highlands_pll} [get_pins {outclk_0 of highlands_pll}]

This is (640*1)/2 = 320 MHz

create_generated_clock -name {outclk_1 of highlands_pll} -source [get_pins {h_pll|highlands_pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 25 -master_clock {Internal VCO of highlands_pll} [get_pins {outclk_1 of highlands_pll}]

This is (640*1)/25 = 25.6 MHz

Regards.