Altera_Forum
Honored Contributor
14 years agoGate level Simulation passes but design fails on target borad
Hello,
I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input stimulus is sine wave of desired frequency. Inputs coefficients decide the cutoff frequency. Expected result is attenuation of sine wave at cut-off freq. Design works fine in RTL as well as Gate level simulation. 1) However, when programmed on target hardware, it fails completly and has output has no attenuation at lower frequencies (100Hz) and wrong beaviour at higher frequencies. 2) I see that fast/slow model results in timing analyses show failures linked to my design. It indicated a different (40MHz) clock domain in the from/to section of the report. 40MHz is used for other sections and I don't use 40 Mhz for this piece of design. ------------------------------------------------------- Please suggest me how to go ahead from gate level simulation to on board running. I am kind of stuck, unable to proceed further. Is there any settings that i need to check. Thanks in advance. Best Regards, VVP