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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks.

The values of coefficients for 100 Hz are as follows:

True a1=1.

Formulasb10.999886916919553b2-1.999747125328010b30.999861787346121a2-1.999747125328010a30.999748704265674

The filter is expected to attenuate the sine wave only at cut-off freq of 100 Hz. I can confirm it happening in RTL & Gate level simulation.

It fails on board ?

Please advice.