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Alberto_G's avatar
Alberto_G
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Gate-Level simulation netlist

Hi all,

I have a hierarchical design with a top file instantiating various submodules, I want to create partitions for each of the submodules so Quartus generates separate netlists for each partition after performing the Analysis & Synthesis and the Fitter, my goal is to then run a Gate-Level simulation of each of the partitions with the results obtained after compiling the whole project.

I recently saw this post that it is exactly what I need: How do I generate gate-level simulation netlists, however this is something only available in the Quartus Prime Pro edition, but I have the Standard edition, is there a way of doing something similar with the Standard edition?

Hdl
Simulation
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi,


    Quartus Standard uses .qxp file for design partition, may check this link https://www.macnica.co.jp/en/business/semiconductor/articles/intel/130493/ on how to export/import design partition (.qxp).

    Since Standard quartus_eda don't support --partition= feature, so have to export partition of submodule, then create wrapper for that submodule (top-level entity), next import partition back to that submodule and last run compilation to generate the netlist.


    Thanks,

    Regards,

    Sheng


1 Reply

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,


    Quartus Standard uses .qxp file for design partition, may check this link https://www.macnica.co.jp/en/business/semiconductor/articles/intel/130493/ on how to export/import design partition (.qxp).

    Since Standard quartus_eda don't support --partition= feature, so have to export partition of submodule, then create wrapper for that submodule (top-level entity), next import partition back to that submodule and last run compilation to generate the netlist.


    Thanks,

    Regards,

    Sheng