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Alberto_G's avatar
Alberto_G
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Gate-Level simulation netlist

Hi all, I have a hierarchical design with a top file instantiating various submodules, I want to create partitions for each of the submodules so Quartus generates separate netlists for each partitio...
Hdl
Simulation
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    Quartus Standard uses .qxp file for design partition, may check this link https://www.macnica.co.jp/en/business/semiconductor/articles/intel/130493/ on how to export/import design partition (.qxp).

    Since Standard quartus_eda don't support --partition= feature, so have to export partition of submodule, then create wrapper for that submodule (top-level entity), next import partition back to that submodule and last run compilation to generate the netlist.


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Quartus Standard uses .qxp file for design partition, may check this link https://www.macnica.co.jp/en/business/semiconductor/articles/intel/130493/ on how to export/import design partition (.qxp).

Since Standard quartus_eda don't support --partition= feature, so have to export partition of submodule, then create wrapper for that submodule (top-level entity), next import partition back to that submodule and last run compilation to generate the netlist.


Thanks,

Regards,

Sheng