Honored ContributorI was wondering how accurate gate level simulation is? I'm seeing different behaviors in simulation and from the synthesized circuit! Does this mean I've done something really really bad in my design, or is it easy enough to create a situation like this? Thanks.
Honored ContributorThe accuracy of the Gate level simulation is usually very good, but it still doesn't 100 % represent the hardware in some situations.
The most If your gate-level simulation is matching your RTL, but the hardware looks like it's doing something else, the most likely cause is: 1) You are not back annotating the SDF file with your gate level simulation. (IE you are doing idealistic timing, and a timing violation is causing the problem) 2) you have a clock crossing boundary that isn't synchronized properly, causing simulation/data mismatch do to metastability. 3) it's possible there's a bug in the fitter/hardware, but unlikely. If none of the above apply to you're case, then I would recommend, trying to debug the issue in the hardware using Signal tap to try to find the source of the problem. PeteHonored ContributorThanks a lot for the info. As a matter of fact I do have two clocks in the design, but as the only connection between two domains is through the Avalon bus, I though it should have already been take care of. Anyways, I'll try with a single clock to see how it goes.
Also, I don't think I fully understand your point about back annotation. Do you mean that I should use "$sdf_annotate" in my .vo file?! Well, that's already included, or did you mean something else?! Again, thanks for all the info. KavehHonored ContributorYou have to use both the design.vho as well as the design.sdo (or was it sdf?) which are placed in the "ModelSIM" directory after synthesis.
Starting Modelsim from the command line, you have to provide this signal delay file too. Modelsim has infos in the help section for the right syntax.
