Gate Level Simulation Accuracy

The accuracy of the Gate level simulation is usually very good, but it still doesn't 100 % represent the hardware in some situations.

The most If your gate-level simulation is matching your RTL, but the hardware looks like it's doing something else, the most likely cause is:

1) You are not back annotating the SDF file with your gate level simulation. (IE you are doing idealistic timing, and a timing violation is causing the problem)

2) you have a clock crossing boundary that isn't synchronized properly, causing simulation/data mismatch do to metastability.

3) it's possible there's a bug in the fitter/hardware, but unlikely.

If none of the above apply to you're case, then I would recommend, trying to debug the issue in the hardware using Signal tap to try to find the source of the problem.

Pete