Gate Level Simulation Accuracy

Thanks a lot for the info. As a matter of fact I do have two clocks in the design, but as the only connection between two domains is through the Avalon bus, I though it should have already been take care of. Anyways, I'll try with a single clock to see how it goes.

Also, I don't think I fully understand your point about back annotation. Do you mean that I should use "$sdf_annotate" in my .vo file?! Well, that's already included, or did you mean something else?!

Again, thanks for all the info.

Kaveh