Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Gate Level Simulation Accuracy

I was wondering how accurate gate level simulation is? I'm seeing different behaviors in simulation and from the synthesized circuit! Does this mean I've done something really really bad in my design...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You have to use both the design.vho as well as the design.sdo (or was it sdf?) which are placed in the "ModelSIM" directory after synthesis.

Starting Modelsim from the command line, you have to provide this signal delay file too. Modelsim has infos in the help section for the right syntax.