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NSriv2's avatar
NSriv2
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7 years ago

FPGA (opencl) code works in emulation (with strict channel depths) but does not work on FPGA (wrong results)

Here is the code (https://drive.google.com/file/d/1QcMYwOPU9onk4CiZx6YFD1pEYjXOSsbY/view?usp=sharing). I am using aoc 17.1 on VLAB

Here are the commands that you can run. (You might need to modify the Makefile according to your aoc setup):

% make compile-emulation

% make compile-host

% make run-emulation

This will pass and give correct results.

FPGA flow:

% make compile-device

% make compile-host

% make run

runs it on FPGA but the results are all 0s

Thanks,

Nitish

3 Replies

  • HRZ's avatar
    HRZ
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Your code does not compile on my environment due to missing channel connections for “A_feeder_channel”. I am using aoc directly on your kernel. Furthermore, you have two writes to the “B_loader_channel” channel. Multiple call sites were not allowed until v17.0 and I would definitely avoid it even now that it is allowed. You are using very complex channeling operations, seemingly with multiple call sites in some places, and you are not enforcing channel ordering as far as I can see. This could very well be the reason for the incorrect output. The emulator fails at emulating concurrency properly; hence, you should not expect it to show concurrency issues that might exists in your kernel correctly.

  • MuhammadAr_U_Intel's avatar
    MuhammadAr_U_Intel
    Icon for Contributor rankContributor
    7 years ago

    Hi Nitish,

    What BSP are you targeting ?

    Have you tried using the latest version of OpenCL compiler 18.1 ?

    Thanks,

    Arslan

  • NSriv2's avatar
    NSriv2
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks for your replies HRZ and MUsman. The problem was multiple read/write channel calls for the same channel. Once I removed that, design started working.