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NSriv2
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7 years ago

FPGA (opencl) code works in emulation (with strict channel depths) but does not work on FPGA (wrong results)

Here is the code (https://drive.google.com/file/d/1QcMYwOPU9onk4CiZx6YFD1pEYjXOSsbY/view?usp=sharing). I am using aoc 17.1 on VLAB Here are the commands that you can run. (You might need to modify t...
NSriv2's avatar
NSriv2
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7 years ago

Thanks for your replies HRZ and MUsman. The problem was multiple read/write channel calls for the same channel. Once I removed that, design started working.