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Altera_Forum's avatar
Altera_Forum
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16 years ago

Fir implementation - Operating Max frequency

Hello,

I have a project which contain 2 independent channelizer. Each channelizer implement 3 fir filters (generated with Fir Compiler v9.0 on Quartus II v9.0 SP1 for FPGA Stratix IV).

When I compil my design with 1 channelizer I get a max frequency equal 207Mhz. If I take off Fir filter, I get a max frequency equal 250Mhz.

When I compil my design with 2 channelizer I get a max frequency equal 140Mhz.

The path with timing error was indicated for fir.

Place and route message :

Info: From Node : top_module_canalisation:top_module_canalisation_inst_1|ddc_4_ch:ddc_4_ch_inst3_map|pfir:pfir_map|pfir_ast:pfir_ast_inst|pfir_st_wr:fircore|pfir_st:u0|msft_mem:tdl_ff_7_n|ram_2pt_var_cen:mem_core|altsyncram:altsyncram_component|altsyncram_aj02:auto_generated|lutrama12~virtual_reg0

Info: To Node : top_module_canalisation:top_module_canalisation_inst_1|ddc_4_ch:ddc_4_ch_inst3_map|pfir:pfir_map|pfir_ast:pfir_ast_inst|pfir_st_wr:fircore|pfir_st:u0|msft_mem:tdl_ff_7_n|ram_2pt_var_cen:mem_core|altsyncram:altsyncram_component|altsyncram_aj02:auto_generated|dataout_reg[12]

I have to compil my design with system clock equal 205MHz and perhaps I have to instantiate 4 channelizers instead of 2. How do I get this frequency?

Complementary information :

Ressource usage for 1 channelizer :

- Comb Alut : 8%

- Mem Alut : 2%

- Dedicated LR: 18%

- Mem blocks : 4%

- DSP blocks : 14%

In attachment, my configuration for fir compiler. Each fir use the same configuration, only Input/Output witdh, rate specification (1 or 2) and coefficients change.

Thanks,

Yvan

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    First, it looks you are using plenty of taps, since your passband looks really nice and stopband attenuation is about 75dB.

    To improve speed margin, I suggest:

    use multipliers instead of distributed arithmetic.

    lower your taps

    add more pipeline

    lower bitwidth to <18 for inputs/outputs
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks Kaz,

    But, I can't implement your suggestion. My project specifications indicate 75dB attenuation and 18/20 for bidwith I/O.

    Max pipeline with fir compiler is 3?

    Yvan
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    why not use the DSP blocks as suggested?

    i also would look at using less bits. you only specify 75 dB dynamic range but are using more bits than required.

    you could also try the DSP Builder Advanced Blockset FIR.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    With my project specifications, I can't use DSP blocks.

    I don't know DSP Builder Advanced Blockset FIR, I will try to use it.

    Thanks