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Altera_Forum
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16 years ago

Fir implementation - Operating Max frequency

Hello, I have a project which contain 2 independent channelizer. Each channelizer implement 3 fir filters (generated with Fir Compiler v9.0 on Quartus II v9.0 SP1 for FPGA Stratix IV). When I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

With my project specifications, I can't use DSP blocks.

I don't know DSP Builder Advanced Blockset FIR, I will try to use it.

Thanks