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Altera_Forum
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16 years ago

Fir implementation - Operating Max frequency

Hello, I have a project which contain 2 independent channelizer. Each channelizer implement 3 fir filters (generated with Fir Compiler v9.0 on Quartus II v9.0 SP1 for FPGA Stratix IV). When I...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks Kaz,

But, I can't implement your suggestion. My project specifications indicate 75dB attenuation and 18/20 for bidwith I/O.

Max pipeline with fir compiler is 3?

Yvan