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Altera_Forum
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16 years ago

Fir implementation - Operating Max frequency

Hello, I have a project which contain 2 independent channelizer. Each channelizer implement 3 fir filters (generated with Fir Compiler v9.0 on Quartus II v9.0 SP1 for FPGA Stratix IV). When I...
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Altera_Forum
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16 years ago

why not use the DSP blocks as suggested?

i also would look at using less bits. you only specify 75 dB dynamic range but are using more bits than required.

you could also try the DSP Builder Advanced Blockset FIR.