Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Fir implementation - Operating Max frequency

Hello, I have a project which contain 2 independent channelizer. Each channelizer implement 3 fir filters (generated with Fir Compiler v9.0 on Quartus II v9.0 SP1 for FPGA Stratix IV). When I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

First, it looks you are using plenty of taps, since your passband looks really nice and stopband attenuation is about 75dB.

To improve speed margin, I suggest:

use multipliers instead of distributed arithmetic.

lower your taps

add more pipeline

lower bitwidth to <18 for inputs/outputs