FIFO:How to slow down the clock Frequency from 50 Mhz

Just checked that the Avalon FIFO memory could not export the "almost full" signal resulting you could not use it as control signal. It is only accessible through IP API or SW control. So, you have to read it from NIOS and then determine the enable signal from PIO. In schematic, connect the "enable" to both counter and write FIFO. Refer to example code for FIFO control in the UG

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf, 20.5.2

Thanks for your reply.

Same thing i have followed.

Enable signal given from PIO

connected enable to both counter and write FIFO. In NIOS same data is printing continuously for certain cycles. Please clarify me how to sort it out.

Design as follows

Counter Verilog Code

module Counter(
    input clk,
	 input enable,
    input reset,
    output reg[31:0] Final_value,
   output  reg trig
    );
    reg[31:0] counter_out;
    reg [7:0] temp=0;
    reg [31:0] counter_result;
    wire temp1;
    wire temp2; 
 
       
   always@(posedge clk)
   begin
    if(reset)
        begin
        trig<=0;
        temp<=0;
        counter_out<=0;
        end
    else if (enable==1'b1)
        begin
        counter_out<=counter_out+1;
        temp<=temp+1;
        if(temp==25)
            begin
            temp<=0;
            trig<=~trig;
            end
  end 
 
	 assign temp1=trig;
	 assign temp2=temp1&&clk;
	 always@(posedge temp2)
	 if(reset)
	    counter_result<=0;   
	  else 
	 begin
        counter_result<=counter_result+1;
     end
  always@(posedge trig)
  if(reset)
       Final_value<=0;  
   else 
  begin
       Final_value<=counter_result;
  end
endmodule

Schematic Design

NIOS CONSOLE, Same data printing For certain cycles.

Have you tried to use and understand the example code and register map given in the FIFO API? What you need to do is

1) ​Set the almost full threshold using initialization : altera_avalon_fifo_init()

2) Monitor the read status of FIFO : altera_avalon_fifo_read_status() and its status description can be referred to 20.5.1 Software control=> "i_status"

Hi

On-Chip Memory Size is 4096

FIFO Depth : 1024

So, have i have set the

 # define ALMOST_EMPTY 1
 # define ALMOST_FULL 1000               //FIFO Depth 1024

The ALMOSTEMPTY and ALMOSTFULL printed in the console are correct.

# define ALMOST_EMPTY 1
 # define ALMOST_FULL 1000               //FIFO Depth 1024
 
int main()
{
 
       	 int result,i=0;
      // 	Reset the FIFO's IRQ History register. *
       	altera_avalon_fifo_clear_event(FIFO_0_IN_CSR_BASE, ALTERA_AVALON_FIFO_EVENT_ALL);
 
    	  int code = ALTERA_AVALON_FIFO_OK;
    	  code= altera_avalon_fifo_init(FIFO_0_IN_CSR_BASE, 0x3F,ALMOST_EMPTY,ALMOST_FULL);
 
    	 IOWR(ENABLE_PIO_BASE, 0, 0x1);
    	 printf("STATUS = %u\n", altera_avalon_fifo_read_status(FIFO_0_IN_CSR_BASE,altera_avalon_fifo_read_status));
    	 while(1)
    	 {
    	 result=altera_avalon_fifo_read_fifo(FIFO_0_OUT_BASE,FIFO_0_IN_CSR_BASE);
     printf("%d\n",result);
    
    	 }
	return 0;
}

In NIOS console,

STATUS =16

result: 0

Suggestion Please

I have attached the Nios Screen-shot.

I am getting all data "0"

printf("STATUS = %u\n", altera_avalon_fifo_read_status(FIFO_0_IN_CSR_BASE,altera_avalon_fifo_read_status));

T​he fifo status isn't right. You have put the same function into the function argument. Refer to table 206, to read back all of bits, use the following command:

printf("STATUS = %u\n", altera_avalon_fifo_read_status(FIFO_0_IN_CSR_BASE,altera_avalon_fifo_status_all));

To debug, please put this status command before starting the transfer and after enabling the transfer.

init_input_fifo();
	IOWR(ENABLE_PIO_BASE, 0, 0x1);
    printf("STATUS = %d\n", altera_avalon_fifo_read_status(FIFO_0_IN_CSR_BASE,    altera_avalon_fifo_status_all));
	level=altera_avalon_fifo_read_level(FIFO_0_IN_CSR_BASE);
	printf("\nLevel=%u\n",level);
	if(level !=0)
	{
	for(i=0;i<=500;i++)
	 {
    	        //result[i]=IORD_ALTERA_AVALON_FIFO_DATA(FIFO_0_OUT_BASE);
    	        data[i]=altera_avalon_fifo_read_fifo(FIFO_0_OUT_BASE, FIFO_0_IN_CSR_BASE);
    	    	printf("data=%lu\t",data[i]);
       }
	}
 
	printf("\n Full=%d\n", altera_avalon_fifo_read_almostfull(FIFO_0_IN_CSR_BASE));
	printf("Empty=%d\n",altera_avalon_fifo_read_almostempty(FIFO_0_IN_CSR_BASE));
}

Now my code is right.