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SS5's avatar
SS5
Icon for Occasional Contributor rankOccasional Contributor
8 years ago

FIFO:How to slow down the clock Frequency from 50 Mhz

once I enable your counter, it is writing at full clock speed to the fifo once the fifo is full, the counter just continues counting by the time it start reading and printing the first value to the...
GuaBin_N_Intel's avatar
GuaBin_N_Intel
Icon for Contributor rankContributor
8 years ago

Just checked that the Avalon FIFO memory could not export the "almost full" signal resulting you could not use it as control signal. It is only accessible through IP API or SW control. So, you have to read it from NIOS and then determine the enable signal from PIO. In schematic, connect the "enable" to both counter and write FIFO. Refer to example code for FIFO control in the UG

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf, 20.5.2