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Altera_Forum's avatar
Altera_Forum
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14 years ago

FIFO usedw signal optimization

Hello,

I have a design that use FIFO to store data. Everything works fine if I check fifo_empty='0' before my FSM starts, but I want to have some space and use fifo_usedw signal. To check the half-full FIFO flag, I use the MSB of the usedw signal, but seems like synthesizer removes the signal, thus my FSM collapses with the whole design. How come rdusedw signal is optimized, if I use it to check for a certain value? 


        case read_state is
            when wait_for_fifo =>                -- Begin fifo read state machine
                coe_ts_valid <= '0';
                coe_ts_start <= '0';
                fifo_rdreq <= '0';
                if(fifo_usedw(13)='1') then    -- fifo_empty='0' -- Check for half full flag, instead of not empty 
                    read_state <= start;
                else
                    read_state <= wait_for_fifo;
                end if;
            when start =>                    -- ack fifo and begin data read
                fifo_rdreq <= '1';
                coe_ts_start <= '1';
                coe_ts_valid <= '1';
                read_state <= count_end;
            when count_end =>                -- check for certain packet number
                fifo_rdreq <= '1';
                coe_ts_start <= '0';
                if(octets_counter=186) then
                    octets_counter <= (others => '0');
                    read_state <= wait_for_fifo;
                    --octets_valid <= '0';
                else
                    octets_counter <= octets_counter + 1;
                    read_state <= count_end;
                end if;
        end case;

FIFO is instantiated like this: 


        aclr         => csi_reset,
        wrclk         => csi_clk,
        rdclk         => csi_clk,
        data(31 downto 24)    => asi_data(7 downto 0),
        data(23 downto 16)    => asi_data(15 downto 8),
        data(15 downto 8)         => asi_data(23 downto 16),
        data(7 downto 0)         => asi_data(31 downto 24),
        rdreq         => fifo_rdreq,
        wrreq         => fifo_wrreq,
        rdempty    => fifo_empty,
        wrfull    => fifo_wrfull,
        q            => coe_ts_data,
        rdusedw    => fifo_usedw

I thought that if I instantiate the rdusedw signal with too short signal or use other short values, then ir could be removed, but I've double checked all the signals, all of them are 14 bits as required.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I don't see anything wrong with the part of code given.

    It is likely your conclusion is wrong. It could be your fifo is always empty in the wait_for_fifo state (never written to till later)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Perhaps the used signal is one bit more narrow than you are expecting. For example if you created an 8 deep FIFO the used signal would be 3 bits wide. There is a new parameterization option (I forget what it's called) which will make the used signal 4 bits wide in that case which is the same as tacking the full bit on the top of the used signal. So if this sounds like what might be happening to you I would look at the documentation and add that extra parameterization option. If you are using an old version of Quartus before this option existed you can do something like this:

    wire [USED_WIDTH:0] true_used;

    wire [USED_WIDTH-1:0] used;

    assign true_used = {full, used};