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Altera_Forum
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14 years ago

FIFO usedw signal optimization

Hello, I have a design that use FIFO to store data. Everything works fine if I check fifo_empty='0' before my FSM starts, but I want to have some space and use fifo_usedw signal. To check the half...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Perhaps the used signal is one bit more narrow than you are expecting. For example if you created an 8 deep FIFO the used signal would be 3 bits wide. There is a new parameterization option (I forget what it's called) which will make the used signal 4 bits wide in that case which is the same as tacking the full bit on the top of the used signal. So if this sounds like what might be happening to you I would look at the documentation and add that extra parameterization option. If you are using an old version of Quartus before this option existed you can do something like this:

wire [USED_WIDTH:0] true_used;

wire [USED_WIDTH-1:0] used;

assign true_used = {full, used};