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Altera_Forum
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14 years ago

FIFO usedw signal optimization

Hello, I have a design that use FIFO to store data. Everything works fine if I check fifo_empty='0' before my FSM starts, but I want to have some space and use fifo_usedw signal. To check the half...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I don't see anything wrong with the part of code given.

It is likely your conclusion is wrong. It could be your fifo is always empty in the wait_for_fifo state (never written to till later)