Feedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended type
I am using Cyclone V 5CGXFC FPGA. And there is 25MHz clock input. I used the 25MHz clock source to generate other frequency clock for platform usage. But when I use PLL, I got the below warning. I don't know how to resolve it.
Warning (12392): Feedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended type
Info (177008): PLL pll_25MHz_cv:pll_25MHz_cv_inst|pll_25MHz_cv_0002:pll_25mhz_cv_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
I created the small example design with Fractional PLL and the IO standrad specified . When I complie ,i got warning given below and which can be overiddern using below KDB link.
Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
Warning (16305): Feedback path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 was routed for regional clock compensation but the clock targeted for compensation was routed as a global clock
Warning (332174): Ignored filter at mi.sdc(37): pll_clk50m could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(38): pll_clk25m could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(39): pll_clk62m5 could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(40): pll_clk20m could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(66): CLK50M_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(66): Argument -group with value CLK50M_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK50M_PLL}
Warning (332174): Ignored filter at mi.sdc(67): CLK25M_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(67): Argument -group with value CLK25M_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK25M_PLL}
Warning (332174): Ignored filter at mi.sdc(68): CLK62M5_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(68): Argument -group with value CLK62M5_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK62M5_PLL}
Warning (332174): Ignored filter at mi.sdc(69): CLK20M_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(69): Argument -group with value CLK20M_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK20M_PLL}
Warning (332049): Ignored set_false_path at mi.sdc(79): Argument <from> is an empty collection
Info (332050): set_false_path -from [get_clocks CLK62M5_PLL] -to [get_clocks CLK62M5_SYS]
Warning (332049): Ignored set_false_path at mi.sdc(80): Argument <to> is an empty collection
Info (332050): set_false_path -from [get_clocks CLK62M5_SYS] -to [get_clocks CLK62M5_PLL]
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