Forum Discussion
Lilian_61
New Contributor
New ContributorFeedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended type
I am using Cyclone V 5CGXFC FPGA. And there is 25MHz clock input. I used the 25MHz clock source to generate other frequency clock for platform usage. But when I use PLL, I got the below warning. I do...
SreekumarR_G_Intel
Frequent Contributor
Frequent Contributorone more thought, would it possible to change the pin allocation and try , Speically to Regional clk pins ?
Thank you,
Regards,
Sree
