New Contributor
Frequent ContributorI created the small example design with Fractional PLL and the IO standrad specified . When I complie ,i got warning given below and which can be overiddern using below KDB link.
Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10232014_332.html?wapkw=Warning%20%28177007%29:
can you check the deign I attcahed and re-create the warning and post it back. This will help me analyze the further.
Thank you,
Regards,
Sree
New ContributorThanks for your help.
I re-compile your project, and I don't find the same warning in report.
The reason I want to resolve this warning, because there are timing analysis issue, and I think this warning have an effect.
I also post part of the other warnings here, may it can offer some help. I tried to fix it myself, but I failed.
The pll_clk50m, pll_clk25m, pll_clk62m5 and pll_clk20m are generated by PLL module.
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Warning (16305): Feedback path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 was routed for regional clock compensation but the clock targeted for compensation was routed as a global clock
Warning (332174): Ignored filter at mi.sdc(37): pll_clk50m could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(38): pll_clk25m could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(39): pll_clk62m5 could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(40): pll_clk20m could not be matched with a port or pin or register or keeper or net or combinational node or node
Warning (332174): Ignored filter at mi.sdc(66): CLK50M_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(66): Argument -group with value CLK50M_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK50M_PLL}
Warning (332174): Ignored filter at mi.sdc(67): CLK25M_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(67): Argument -group with value CLK25M_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK25M_PLL}
Warning (332174): Ignored filter at mi.sdc(68): CLK62M5_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(68): Argument -group with value CLK62M5_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK62M5_PLL}
Warning (332174): Ignored filter at mi.sdc(69): CLK20M_PLL could not be matched with a clock
Warning (332049): Ignored set_clock_groups at mi.sdc(69): Argument -group with value CLK20M_PLL could not match any element of the following types: ( clk )
Info (332050): set_clock_groups -exclusive -group {CLK20M_PLL}
Warning (332049): Ignored set_false_path at mi.sdc(79): Argument <from> is an empty collection
Info (332050): set_false_path -from [get_clocks CLK62M5_PLL] -to [get_clocks CLK62M5_SYS]
Warning (332049): Ignored set_false_path at mi.sdc(80): Argument <to> is an empty collection
Info (332050): set_false_path -from [get_clocks CLK62M5_SYS] -to [get_clocks CLK62M5_PLL]
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