Forum Discussion
Lilian_61
New Contributor
New ContributorFeedback return path used by PLL(s) in location FRACTIONALPLL_X68_Y54_N0 is not of the recommended type
I am using Cyclone V 5CGXFC FPGA. And there is 25MHz clock input. I used the 25MHz clock source to generate other frequency clock for platform usage. But when I use PLL, I got the below warning. I do...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorCan I know what is the mode of the PLL used in the design ?
(ie Normal mode ; Zero Delay Buffer mode or No Compensation mode )
Would it possible to share the your setting and pin used for Inclk0 ?
Thank you,
Regards,
Sree
Lilian_61New Contributor
New ContributorThe PLL used is Normal Mode.
Below is physical connection. The CLK25M_TXCO_FPGA1_AC_P/N is differential clock generated by TCXO.
In FPGA setting, the IO standard is set as DIFFERENTIAL LVPECL, and the CLK25M_TCXO_FPGA1_AC_P is the refclk of PLL module.
