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rdruyer's avatar
rdruyer
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7 years ago

Experiencing Quartus unexpected error when compiling a partially reconfigurable design

Hi,

We are experiencing an unexpected error with Quartus when compiling a partially reconfigurable custom design for ARRIA 10.

First, we successfully followed the Altera AN770. We are able to partially reconfigure the FPGA through the JTAG port with the design example.

The LEDs frequency of our custom board is modified after the partial reconfiguration as we expect it.

But when we are trying to make a custom design using the same procedure (AN770), Quartus is experiencing an unexpected error during the compilation. The error is actually triggered during the execution of "flow.tcl" script.

The error description from the Quartus console suggests us to consult report file(s) to have more information about this error. Unfortunately we are unable to find any references of this in the generated .rpt files.

The quartus project attached with my message is a simplified version of our real design, but still has the same error when running "flow.tcl" script.

The two personas "bloc_config" & "bloc_config_empty" of the partition "bloc_config" are identical but it may be not the error source.

We tried different configuration, like adding a freeze control to all the partition signal outputs. But we are still getting the same error.

We will be glad to know the cause of this error.

Thanks

Quartus Prime Pro - 17.1.1 Build 273.

ARRIA 10 GX (10AX115N4F45E3SG)

AN770 : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an770.pdf

Remy D.

Best regards

8 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    Can you post your flow.tcl file? Also, try running it from the command line (quit Quartus first) as mentioned in the app note instead of through the GUI.

  • PLe_Q1's avatar
    PLe_Q1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks for you answer, you can find the .tcl file into the project archive directory : DDR3_RECONFIG/top/place_route/a10_partial_reconf/

    I have only modified the "setup.tcl" following the AN770 guideline.

    "flow.tcl" script is untouched since its generation with the NIOS 2 SHELL command "quartus_sh --write_flow_template -flow a10_partial_reconfig"

    As you suggested, I've tried to execute the script from the NIOS 2 SHELL after exiting Quartus but it doesn't still the issue. I continue to investigate about these errors and I'll keep you in touch if I find any solution.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    I don't really want to download your whole project. Can you post your setup.tcl?

  • rdruyer's avatar
    rdruyer
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    7 years ago

    Here is "setup.tcl" content:

    define_project top

    define_base_revision top

    define_pr_impl_partition -impl_rev_name top_pr_alpha \

    -partition_name pr_partition \

    -source_rev_name top_default

    define_pr_impl_partition -impl_rev_name top_pr_bravo \

    -partition_name pr_partition \

    -source_rev_name top_empty

    I don't think that the error come from this file because if the variables like "define_project" or "partition_name" do not correspond to anything in the project I get a clear error message.

    I've submitted a support ticket, the person from Altera suggested me to try the PR flow with the last Quartus version 18.1 Pro.

    I'll keep you informed if it works or I get a different error message .

  • PLe_Q1's avatar
    PLe_Q1
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    7 years ago

    Hi Arslan,

    Thank you for your answer.

    First, just to keep you informed my project is not working either with Quartus 18.1 Pro (done following AN797). The compilation of any of the persona is crashing without any explicit error message.

    I am totally agree with you, since "blinking_led" is working with Quartus 17.1 & Quartus 18.1 something in my project is making the compilation to crash.

    I have already disabled the NIOS debug port since we cannot have JTAG controller in the partially reconfigurable partition (unless using a dedicated bridge). Also, no device PIN is directly connected to the reconfigurable partition as specified in application notes & user guides.

    I have also tried to only put dummy logic into the partition (entity inputs are registered and redirected to entity outputs) but it is not working either.

    For the moment, I suspect that the DDR3 controller core is maybe the reason of these crashes. I'll try to compile my project without this core and I will keep you informed.

    Any help from your part will be much appreciated.

    Best regards

  • PLe_Q1's avatar
    PLe_Q1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Just to clarify, I am the same person behind "RDruy" and "PLe Q1".

    "PLe Q1" is the account we use to contact Altera support in my company department and "RDruy" is my personal account. I just keep forgetting to sign in with "RDruy" before answering to the topic.

    Thanks for you help

  • MuhammadAr_U_Intel's avatar
    MuhammadAr_U_Intel
    Icon for Contributor rankContributor
    7 years ago

    Are you able to proceed with this ?

    Any updates after removing the DDR controller / NIOS from the project ?

    Thanks.