Forum Discussion

New Contributor

7 years ago

Experiencing Quartus unexpected error when compiling a partially reconfigurable design

Hi, We are experiencing an unexpected error with Quartus when compiling a partially reconfigurable custom design for ARRIA 10. First, we successfully followed the Altera AN770. We are able to parti...

full_console_error.txt1 KB

ddr3_pr_project.zip2.7 MB

MuhammadAr_U_Intel

Contributor

7 years ago

Hi,

Yes please follow the latest flow you may refer to application note AN797 for that.

https://www.intel.com/content/altera-www/global/en_us/index/documentation/ihj1482170009390.html

Since you have already tested the LEd blinking example, I suspect this is something to do with you design (PR Partition)

Can you check if you disable the NIOS debug port ?

Thanks,

Arslan

Forum Discussion

Experiencing Quartus unexpected error when compiling a partially reconfigurable design

Recent Discussions

timing violation fix

Issues with downloading

Quartus Prime Lite 25.1 License Error - "Unable to checkout a license" (SALT_LICENSE_SERVER)

Quartus Prime Pro 26.1 - Where to find Documentation of new Signaltap features

Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10