New Contributorwe dont know what happen in agliex-F device to use the LVDS RX IP
Quartus pro 22.4
if we export the LVDS RX IP parallel date to IO this error will disappear.
Frequent ContributorHi there,
Could u please show the complete error~
Frequent ContributorHi~ Anyupdate?
Frequent ContributorHi there
What is the version of quartus~
By the way, I advise u check the ports of par port and add the bit width for it. In some versions of quartus, it need you add the bit width for parameters
Frequent ContributorHi there,
Any update~
ContributorHi@WZ2 and @HongLiang ,
I'm having a similar compile error on Quartus Pro 21.3 for my project in Cyclone 10. I've set the number of channels to 24 and the serdes factor to 7 in the LVDS IP, but I'm getting the error message below and couldn't figure out why. The message says that the output port is disconnected, but I connected that to another component in the Platform Designer... If you already know the solution, I'd be very appreciated when you share it with me!
Cheers
Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[7].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[7].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[1].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[1].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[6].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[6].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[15].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[15].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[3].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[3].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[2].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[2].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[5].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[5].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[4].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[4].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[13].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[13].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[14].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[14].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[16].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[16].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[12].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[12].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[10].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[10].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[11].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[11].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[8].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[8].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[23].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[23].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[22].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[22].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[17].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[17].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[18].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[18].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[19].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[19].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[20].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[20].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[21].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[21].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[0].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[0].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port. Error: Failed to synthesize partition
