ContributionsMost RecentMost LikesSolutionsRe: HDMI example an not change the device in V22.4 for aglixe FPGA Hi maybe you guys can try to find a way or step to create the AGFB027R31C2E1V HDMI example Re: HDMI example an not change the device in V22.4 for aglixe FPGA Hi May I clarify with you below items: Q1. Which Quartus version you are using? 22.4 Q2. Which OPN you intend to use? there are 2 OPN we will use AGFB027R31C2E1V AGIB027R31B1I1V Q3. May i know which design example variant and settings you want to generate? we will need HDMI TX /RX SDI TX/RX DP TX/RX I try to use op1(intel recommand) step1. create a whole new project for AGFB027R31 step2. call the HDMI IP -->set the hdmi in TX and AXIS mode to generate setp3. generate the example IP but I still see the example target ID is not the same as the project OPN Re: Agilex DP IP integration with F-tile PHY some signals mismatch Hi Q1. Did you generate your design from design example? YES please see https://community.intel.com/t5/Intel-Quartus-Prime-Software/Does-the-Agliex-F-support-Display-port-IP/m-p/1456902#M77329 Q2. Did you manage to compile the design? Any errors message or violation? Yes Q3. Could you share with us your .qar file? please see the attached file we don't know how to regenerate the F-tile IP It's not a standard IP file. BR Hong Re: Does the Agliex F support Display port IP ? Hi Yes, when we turn-on the AXISWP on TX and RX. An example will be created. but P&R this example will error and we don't know how to regenerate the F-tile IP. it seems a predesign IP manually from the Example. BR Hong Re: Does the Agliex F support Display port IP ? Hi Q1.Did you enable/turn on the parameter settings as above? NO cuz I turn-on the AXIS WP Q2.May I know which OPN and Quartus version that you are using? set_global_assignment -name DEVICE AGFB027R31C2E1V Q3.May I know which design example you are trying to generate? As for DisplayPort SST Parallel Loopback with AXIS Video Interface Re: Error(129015): Output port PAR_OUT on atom "lvds_rx_sp|u0_single|lvds_0|core|arch_inst|rx_channels[2 Hi sorry I upload a wrong file This is the correct file. Re: Error(129015): Output port PAR_OUT on atom "lvds_rx_sp|u0_single|lvds_0|core|arch_inst|rx_channels[2 Hi The attached file is the log file Its weir! HDMI example an not change the device in V22.4 for aglixe FPGA We try to use the EVB to test the HDMI function We generate the HDMI EXAMPLE from Quartus 22.4 following the HDMI doc step we change the device ID in step 10 but the result is still kept in the default device. Can anyone tell me how to change the HDMI example default device? If I change the device after step 11. The Quartus 22.4 will report P&R error Error(129015): Output port PAR_OUT on atom "lvds_rx_sp|u0_single|lvds_0|core|arch_inst|rx_channels[2 we dont know what happen in agliex-F device to use the LVDS RX IP Quartus pro 22.4 if we export the LVDS RX IP parallel date to IO this error will disappear. Does the Agliex F support Display port IP ? we Try to build DP1.4 on the Agliex-F but we can not find the example from the IP Does the Agilex-F support the Display Port IP ? but we can find the design in the Agilex-I. but the F-tile PHY IP had been modified manually in the example. I can not just move it to Algilex-F.