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Altera_Forum's avatar
Altera_Forum
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11 years ago

Error while debugging using system-console

Hi,

I am trying to debug a design containing Nios II on a Stratix V FPGA. When debugging with system-console, while trying to do a memory read, i get the following error :

% master_read_memory $nios 0x00000 4

error: master_read_memory: com.altera.systemconsole.internal.plugin.jtag.oci. Nios2DebugException: Target is broken and needs to be reset

while executing

The RAM in my design doesn´t seem to work. How can I solve this?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Did you start system console from QSYS? If not, try opening your project in QSYS and starting system console from there. Also, make sure the JTAG server is running and it recognizes the JTAG chain.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I have not used system console with NIOs. However, just to share experience using xcvr toolkit which is running on system console as well. You might also want to verify if the system console has been successfully linked to your design before doing the read/write.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Hi,

    I am trying to debug a design containing Nios II on a Stratix V FPGA. When debugging with system-console, while trying to do a memory read, i get the following error :

    % master_read_memory $nios 0x00000 4

    error: master_read_memory: com.altera.systemconsole.internal.plugin.jtag.oci. Nios2DebugException: Target is broken and needs to be reset

    while executing

    The RAM in my design doesn´t seem to work. How can I solve this?

    --- Quote End ---

    Did you stop the NIOS operation before the command being executed? I guess it corrupts in the middle of NIOS firmware.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I did stop the NIOS before executing the read.

    Also, I started the system-console from Qsys
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Are you getting any error if reading other module's register mapping in your design? Where did you get the RAM controller?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I tried to do something else for bedugging. I made a Nios I application and BSP from template and tried to run the memory test (template) on my design. While doing build project, I get the error :

    undefined reference to `__alt_invalid'

    What does this mean?