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Steven_H's avatar
Steven_H
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Error running TCL script after upgrading from Pro 22.4 to Pro 23.3

I’ve attached the files needed to reproduce the error. This TCL script was working in 22.4.

You need to set up Quartus Pro 23.3 environment variables first and then run the following command in the terminal:

quartus_sta -t Synthesis.tcl

Weirdly enough, if I run the same commands in the TCL console in Quartus itself, it has no problem running the “get_names” command. This error is very cryptic as it gives no indication as to why it didn’t work.

Hdl
Timing
  • TingJiangT_Intel's avatar
    TingJiangT_Intel
    1 year ago

    Hi there, please use the following tcl:


    load_package flow

    load_package report

    #load_package sta


    project_new toplevel_Characterization -overwrite

    set_global_assignment -name TOP_LEVEL_ENTITY toplevel_Characterization

    set_global_assignment -name DEVICE 1SD110PJ1F43E1VG

    foreach sfile [list BlockSubsystem.vhd toplevel_Characterization.vhd] {

    set_global_assignment -name VHDL_FILE $sfile

    }

    set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON

    execute_module -tool map


    set pin_ids [get_names -filter In* -node_type pin]

    foreach_in_collection pin_id $pin_ids {

    set pin_name [get_name_info -info full_path $pin_id]

    set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON

    }


    set pin_ids [get_names -filter Out* -node_type pin]

    foreach_in_collection pin_id $pin_ids {

    set pin_name [get_name_info -info full_path $pin_id]

    set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON

    }


    export_assignments

    execute_module -tool map

    execute_module -tool fit -args --plan

    project_close


    BTW, instead of using quartus_sta, please use quartus_sh -t Synthesis.tcl .


8 Replies

  • TingJiangT_Intel's avatar
    TingJiangT_Intel
    Icon for Contributor rankContributor
    1 year ago

    Hi there, please use the following tcl:


    load_package flow

    load_package report

    #load_package sta


    project_new toplevel_Characterization -overwrite

    set_global_assignment -name TOP_LEVEL_ENTITY toplevel_Characterization

    set_global_assignment -name DEVICE 1SD110PJ1F43E1VG

    foreach sfile [list BlockSubsystem.vhd toplevel_Characterization.vhd] {

    set_global_assignment -name VHDL_FILE $sfile

    }

    set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON

    execute_module -tool map


    set pin_ids [get_names -filter In* -node_type pin]

    foreach_in_collection pin_id $pin_ids {

    set pin_name [get_name_info -info full_path $pin_id]

    set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON

    }


    set pin_ids [get_names -filter Out* -node_type pin]

    foreach_in_collection pin_id $pin_ids {

    set pin_name [get_name_info -info full_path $pin_id]

    set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON

    }


    export_assignments

    execute_module -tool map

    execute_module -tool fit -args --plan

    project_close


    BTW, instead of using quartus_sta, please use quartus_sh -t Synthesis.tcl .


    • Steven_H's avatar
      Steven_H
      Icon for New Contributor rankNew Contributor
      1 year ago

      Thanks for the response, Ting Jiang.

      That resolves the error I'm hitting, but now I hit a new error further down my workflow which is the reason I was using quartus_sta.

      Tcl error: ERROR: Quartus Prime Tcl command "create_timing_netlist" is only available for use in the following executables:
      quartus_fit
      quartus_sta

      I need to do a detailed timing analysis along various register paths, but I only need to do the timing on rough synthesis estimates and not a design that is fitted to the FPGA (since we run synthesis many times and I imagine quartus_fit will have a significant time penalty).

      Do you have any suggestions?

      Steven

    • Steven_H's avatar
      Steven_H
      Icon for New Contributor rankNew Contributor
      1 year ago

      Thanks for the pointer. I've updated my 2-step script to call quartus_sh for synthesis and then quartus_sta on the same project after that when we create the timing netlist and do the timing analysis. I previously had updated both quartus_sta calls to quartus_sh which gave that error. I only should update the first one as suggested.

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Also,


    You should use


    quartus_sh -t Synthesis.tcl instead of quartus_sta



  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Not sure if you have further question on this? If no, we shall close this thread.


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a follow up question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.