Forum Discussion
New ContributorError running TCL script after upgrading from Pro 22.4 to Pro 23.3
Hi there, please use the following tcl:
load_package flow
load_package report
#load_package sta
project_new toplevel_Characterization -overwrite
set_global_assignment -name TOP_LEVEL_ENTITY toplevel_Characterization
set_global_assignment -name DEVICE 1SD110PJ1F43E1VG
foreach sfile [list BlockSubsystem.vhd toplevel_Characterization.vhd] {
set_global_assignment -name VHDL_FILE $sfile
}
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
execute_module -tool map
set pin_ids [get_names -filter In* -node_type pin]
foreach_in_collection pin_id $pin_ids {
set pin_name [get_name_info -info full_path $pin_id]
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
set pin_ids [get_names -filter Out* -node_type pin]
foreach_in_collection pin_id $pin_ids {
set pin_name [get_name_info -info full_path $pin_id]
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
execute_module -tool map
execute_module -tool fit -args --plan
project_close
BTW, instead of using quartus_sta, please use quartus_sh -t Synthesis.tcl .
ContributorHi there, please use the following tcl:
load_package flow
load_package report
#load_package sta
project_new toplevel_Characterization -overwrite
set_global_assignment -name TOP_LEVEL_ENTITY toplevel_Characterization
set_global_assignment -name DEVICE 1SD110PJ1F43E1VG
foreach sfile [list BlockSubsystem.vhd toplevel_Characterization.vhd] {
set_global_assignment -name VHDL_FILE $sfile
}
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
execute_module -tool map
set pin_ids [get_names -filter In* -node_type pin]
foreach_in_collection pin_id $pin_ids {
set pin_name [get_name_info -info full_path $pin_id]
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
set pin_ids [get_names -filter Out* -node_type pin]
foreach_in_collection pin_id $pin_ids {
set pin_name [get_name_info -info full_path $pin_id]
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
execute_module -tool map
execute_module -tool fit -args --plan
project_close
BTW, instead of using quartus_sta, please use quartus_sh -t Synthesis.tcl .
Steven_HThanks for the response, Ting Jiang.
That resolves the error I'm hitting, but now I hit a new error further down my workflow which is the reason I was using quartus_sta.
Tcl error: ERROR: Quartus Prime Tcl command "create_timing_netlist" is only available for use in the following executables:
quartus_fit
quartus_staI need to do a detailed timing analysis along various register paths, but I only need to do the timing on rough synthesis estimates and not a design that is fitted to the FPGA (since we run synthesis many times and I imagine quartus_fit will have a significant time penalty).
Do you have any suggestions?
Steven
