New ContributorError message while trying to compile a project with one LVDS output.
Hi, i have been trying to test LVDS functionality by creating an output as reg (not wire) and then setting its' val with a non-blocking assignment inside an always loop.
I started by creating a single output called lvds_out. I then created the symbol by running File->Create/Update->Create symbol files for current file. I inserted the symbol in the block-diagram form and run Analysis & elaboration. Then i got into Pin planner and i saw the pin that i created (as i should). As soon as i selected LVDS and hit ENTER the negative output was selected for me. I compiled and i got the error messages that you see in the attached images.
I am obviously doing something wrong. What is the process when creating a LVDS output? Is the logic same when creating LVDS inputs? Should i be having 2 outputs in my verilog (and accordingly in the block-diagram) instead of one?
Can you pls help me out here?
Verilog code:
//It has a single clock input and a 32-bit output port
module lvds_buffer (
input clk,
output reg lvds_out
);
// on positive clock edge
always @ (posedge clk) begin
// Reverse level on every positive edge
lvds_out <= ~lvds_out;
end
endmodule
