Forum Discussion
ETsac
New Contributor
7 years agoError message while trying to compile a project with one LVDS output.
Hi, i have been trying to test LVDS functionality by creating an output as reg (not wire) and then setting its' val with a non-blocking assignment inside an always loop. I started by creating a sin...
ETsac
New Contributor
7 years agoThanks for your message Sree. It's all clear to me now.
Best regards
Manos